飞思卡尔半导体（中国）有限公司苏州研发实习生招聘信息
飞思卡尔半导体总部位于美国德克萨斯州奥斯汀市，其设计、研发、生产及销售机构遍布20 多个国家和地区。在创新、质量和注重实效的企业文化引领下，全球 18,000 名员工齐心协作、锐意进取。秉承让世界更智能的理念，我们始终是嵌入式处理解决方案的领导者。飞思卡尔在嵌入式处理解决方案领域处于全球领先地位，推动汽车电子、消费类电子、工业电子以及网络设备市场向前发展。从微处理器和微控制器，到传感器、模拟 IC 以及连接器件 ——我们的技术和产品始终为创新奠定基础，让世界变得更环保、更安全、更健康，让人们的联系更加紧密。
飞思卡尔（中国）近期发布大量实习生职位（详见后文的职位列表），此次实习生职位只针对2015年及以后毕业的硕士研究生，欢迎大家踊跃报名~~
本次实习期为6-12个月，实习生日后很有可能成为飞思卡尔的正式成员，还等什么？赶紧报名！
报名方式：大家可以将自己的简历以“工作地点-职位名称-毕业年份”为标题将简历发送至：campus@freescale.com
另外，我们的招聘职位都是实时更新的，欢迎大家多多关注我们：http://www.freescale.com/zh-Hans/webapp/sps/site/homepage.jsp?code=CAREERS
具体职位信息如下：
1. IC Design andVerification InternLocation:Suzhou Responsibilities:- Designsand develops digital circuits for Micro-controller (MCU).- Verificationin module level and Chip level; define and execute verification plan with fullfunctional coverage.- Involvedin the Digital IP design and verification, joins the SoC development for 8bits, 32 bits MCU.- Doing RTLcoding, integration and verification.- Doingsimulation in Gate Level, transistor Level (full-chip spice).- Createfunction test patterns for testing engineering. Requirements:- Bachelorsor Master Degree or University Degree or equivalent from Electronic, Electricalor Computer Science.- Wellcommunication and Inter-person skill.- Goodlanguage skill in English, Pass CET-6.- Haveknowledge about EDA simulation and synthesis tool as well as VLSI design flow. - Goodknowledge in Verilog, VHDL, System C or E language.- Have usedEDA tool from Cadence, Synopsis, Mentor digital and/or analog developing- Haveknowledge about Computer Architecture, 8bit, 16bit or 32bit Micro-controller orMicro-processer.- Preferknow-how of ARM or AHB bus system.- Preferexperience of formal verification with property scheme.- Basicknowledge of Analog and Mix-signal design and simulation. 2.EDA tool Develop Intern Location:Suzhou Responsibilities:- Developsand optimizes EDA tool for better performance.- Integratenew algorithm into existing Simulation and Develop EDA tool.- Integratemeasurement to evaluate the Engineering quality. Requirements:- Bachelorsor Master Degree or University Degree or equivalent from Software Engineering,Math or Computer Science.- Wellknowledge of C and scripts language programming;- Solidbackground in math, especially in probability statistics and discretemathematics;- Goodexperience of MatLab, and prefer experience of Minitab software.- Haveexperience with Unix system.- Haveknowledge about EDA simulation tool as well as VLSI design flow. - Known EDAtool from Cadence, Synopsis, Mentordigital and/or analog developing.- Wellcommunication and Inter-person skill.- Goodlanguage skill in English, Pass CET-6. 3.Digital IP Design & Verification InternLocation:Suzhou Responsibilities:- VerilogRTL coding for digital IP;- IP andPlatform level testbench setup, IP verification with both BFM and C;- Regressionand random testing on RTL and gates;- Asynchronousclock boundary crossing analysis and ECO process.- Debuggingcomplex system level simulations. Requirements:- GraduateStudent in Electrical or Computer Engineering.- Familiarwith digital circuit design and analysis.- Familiarwith Verilog HDL.- Backgroundin C program language- Familiarwith computer architecture and organization is a plus- Experienceon synthesis, timing analysis and formal verification is a plus- Familiarwith SystemVerilog is a plus- Familiarwith UVM is a plus- Workingknowledge of Perl scripting and Makefiles is a plus- Workingknowledge of UNIX/Linux operating systems a plus 4.Analog/Mixed Signal Design Engineer Intern
Location: Suzhou Responsibilities: - Responsiblefor analog / mixed-signal IPdesign forMCU product development- IndependentIP schematic design / analog & mix-signal simulation/ layout design / IPview generation / technical documentation- Work withSoC / Backend team on IP integration.- Work withtest/validation/qualification team on IP validation, characterizations andfailure analysis.
Requirements:- MasterDegree in Electrical or Computer Engineering.- Familiarwith analog/mix-signal IC schematic and layout design - Familiarwith design EDA tool: Hspice/Spectre, Virtuso,Calibre, Assura, QRC;- Familiarwith lab equipments andsiliconvalidation /debug flow - Experiencein power management module design ( high accuracy bandgap /LDO/DC-DC/…) is aplus- Experiencein data conversion module design ( ADC/DAC) is a plus- Experiencein clock generation module design ( crystal osc/ relaxation osc/ /PLL/FLL/..)is a plus- Experiencewith mix-signal circuit modeling & simulation is a plus- Goodcommunication skills and team work - Good oraland written English skills 5.DFT (Design for Test) Engineer InternLocation:SuzhouResponsibilities: - Responsiblefor whole chip DFT architecture definition and DFT planning for complex SoCdesign; - Performdesign implementation and verification on test modules, scan insertion, testcompression, Memory Build In Self Test, Logic Build In Self Test, JTAG/Boundaryscan. - Beresponsible to improve the testability of IP and chip to meet test coveragerequirement. - Beresponsible for scan pattern generation, BIST and boundary scan patterngeneration and verification.- Serve asthe focal point for the SoC team in interfacing with Test Engineer and ProductEngineer to define the DFT requirement, deliver test patterns and providesupport on silicon test debug. Requirements: - Bachelor,Master on Electronics, Communications, Microelectronics Engineering andComputer Science.- Stronglogic design and verification background with good debugging capability,Experience in digital design with good knowledge of SoC design flow, includingRTL coding, simulation, synthesis, DFT and silicon test. - Familiarwith industrial standard DFT methodology and tools, Experience on scan,ATPG, memory BIST, LBIST, T, Boundary scan, etc.- Analog/flashdesign knowledge/background will be a strong plus.- Knowledgein ATEand experience in silicon validation on tester will be plus. - Nice tohave skills: script language like perl, tcl. 6.IC Backend design internLocation:SuzhouResponsibilities:- Backendteam of SDC MPG participates in chip level (from RTL-synthesis to GDS-TO) andblock level backend design for SOC designs.- Responsiblefor low power embedded MCU soc design.- Major onchip and block level CPF definition, Logic/physical synthesis, Clock treesynthesis, place and routing, STA timing closure.- Responsiblefor Die size estimation, floor-planning, power planning and power analysis. - Responsiblefor chip-finishing, DFM, DRC/LVS physical verification.
Requirements:- BSEE orhigh required. - team workspirit, communication skills, and enterprise.- Engineeringwith several years experience in synthesis, timing closure. - Relevantproject experience for synthesis, timing closure … soc physicalimplementation activities. - Experienceusing backend EDA tools; i.e. Cadence EDI, ETS, EPS, virtuoso…., CalibreDRC/ERC/LVS, etc similar tools. - Relevantprocess and technology experience.- Relevantexperience for integration of embedded processors, flash memory. - Goodgrasp of C/C++, Perl/TCL, and skill scripts in Linux/Unix environment 7.Validation InternLocation:SuzhouResponsibilities:- Applyskills and knowledge in both hardware and software to perform Pre or PostSilicon validation tasks for Freescale microcontroller products- To definethe validation plan, and create or execute validation test - Designand layout the validation board to bring up new system for fresh IC- Work withother cross functional teams in Chinaand oversea to specify, verify and improve SoC quality and timeliness toproduction
Requirements:- Master orBachelor Degree, electronic or microelectronic- Workingknowledge in C/C++, Makefile- Big pluswith experience in ARM M0, M0+ and M4 based MCU- Big pluswith experience in IAR and CodeWarrior debugger Tool- With theFPGA development experience is plus- Fluent inwriting and speaking English - Can workefficiently either in a team or an independent environment 8.Android SW Engineer InternLocation:Suzhou & ShanghaiResponsibilities:- Be responsible to run Android CTS on i.MX Androidplatform- Assist on analyzing Android CTS failure - Improve the automation tool and coverage ofunit tests on i.MX Android platform- Investigate APK compatibility on i.MX AndroidplatformRequirements:- Major in computer science, electronic engineeringor equivalent- Strong programming skills on C/C++- Java programming skill will be a good plus- Experience with Android development will be a goodplus- Experience with embedded software development willbe a good plus- Experience with GIT is desired.- Good communication skills- Good oral and written English skills 9.Linux SW Engineer InternLocation:Suzhou & ShanghaiResponsibilities:- Be responsible to Linux SW design and test on i.MXplatform- Assist on analyzing Linux test failure - Improve the automation tool and coverage of unittests on i.MX platform- Help to create related documents for i.MX linuxplatform Requirements: - Major in computer science, electronic engineeringor equivalent- Strong programming skills on C/C++- Java programming skill will be a good plus- Experience with Android development will be a goodplus- Experience with embedded software development willbe a good plus- Experience with GIT is desired.- Good communication skills- Good oral and written English skills 10.MCU SW Engineer InternLocation:Suzhou & ShanghaiResponsibilities: - Develop /maintain core MCU S/W (RTOS porting, driver, stack and bare metal S/Wdevelopment etc) for Freescale Microcontroller portfolio.- Design,develop and execute the test cases to ensure the quality of the MCU S/W.- Profile /optimize the performance of the system / driver / stack.- Bug fixfor the issues in the driver / stack / test code. Requirements: - MSDegree, EE or Computer Science or related field- Goodunderstanding of general MCU architecture and peripherals- Solidknowledge on Assembly or C/C++ programming and embedded system- Familiarwith embedded OS like MQX, ucosII, ucLinux, Linux or other RTOS- Familiarwith shell script is a plus- Experiencewith TCP/IP or USB is a plus- Experiencewith ARM based MCU is a plus- FluentEnglish read/write/speak capability
好多。。 支持一下 熟悉的飞思卡尔~~~
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